Multiple IBM ISS Proventia Series products, including the A, G, and M series, do not properly handle certain full-width and half-width Unicode character encodings, which might allow remote attackers to evade detection of HTTP traffic.
Conclusion & alert: CVE-2007-2690 is rated High Risk (65/100): CVSS High severity, with medium exploitation likelihood (EPSS 4.27%). Core evidence: EPSS rose +2.77% over the last day, indicating growing attacker interest. Mandatory action: High exploitation likelihood—assess exposure and prioritize remediation.
Risk is dynamic; we continuously reassess and refresh what is shown on this page as upstream context changes.
EPSS lead: Daily EPSS estimates relative likelihood of exploitation; percentile ranks this CVE among scored vulnerabilities (higher = more severe relative rank).
| # | Date | Old EPSS score | New EPSS score | Delta (New - Old) |
|---|---|---|---|---|
| 1 | 2026-02-21 | 1.50% | 4.27% | +2.77% |
| 2 | 2026-01-02 | 1.23% | 1.50% | +0.27% |
| 3 | 2025-06-11 | — | 1.23% | — |
Full EPSS history (12 records total)
CVSS metrics for this CVE.
| Base score | Version | Severity | Vector | Exploitability | Impact | Score source |
|---|---|---|---|---|---|---|
| 7.8 | 2.0 | HIGH |
|
10.0 | 6.9 | [email protected] |
| Vendor | Product | Version | Raw CPE |
|---|---|---|---|
| iss | proventia_a_series_xpu | <= 22.10 | cpe:2.3:h:iss:proventia_a_series_xpu:*:*:*:*:*:*:*:* |
| iss | proventia_a_series_xpu | 20.11 | cpe:2.3:h:iss:proventia_a_series_xpu:20.11:*:*:*:*:*:*:* |
| iss | proventia_a_series_xpu | 22.1 | cpe:2.3:h:iss:proventia_a_series_xpu:22.1:*:*:*:*:*:*:* |
| iss | proventia_a_series_xpu | 22.2 | cpe:2.3:h:iss:proventia_a_series_xpu:22.2:*:*:*:*:*:*:* |
| iss | proventia_a_series_xpu | 22.3 | cpe:2.3:h:iss:proventia_a_series_xpu:22.3:*:*:*:*:*:*:* |
| iss | proventia_a_series_xpu | 22.4 | cpe:2.3:h:iss:proventia_a_series_xpu:22.4:*:*:*:*:*:*:* |
| iss | proventia_a_series_xpu | 22.5 | cpe:2.3:h:iss:proventia_a_series_xpu:22.5:*:*:*:*:*:*:* |
| iss | proventia_a_series_xpu | 22.6 | cpe:2.3:h:iss:proventia_a_series_xpu:22.6:*:*:*:*:*:*:* |
| iss | proventia_g_series_xpu | <= 22.11 | cpe:2.3:h:iss:proventia_g_series_xpu:*:*:*:*:*:*:*:* |
| iss | proventia_g_series_xpu | 22.1 | cpe:2.3:h:iss:proventia_g_series_xpu:22.1:*:*:*:*:*:*:* |
| iss | proventia_g_series_xpu | 22.2 | cpe:2.3:h:iss:proventia_g_series_xpu:22.2:*:*:*:*:*:*:* |
| iss | proventia_g_series_xpu | 22.3 | cpe:2.3:h:iss:proventia_g_series_xpu:22.3:*:*:*:*:*:*:* |
| iss | proventia_g_series_xpu | 22.4 | cpe:2.3:h:iss:proventia_g_series_xpu:22.4:*:*:*:*:*:*:* |
| iss | proventia_g_series_xpu | 22.5 | cpe:2.3:h:iss:proventia_g_series_xpu:22.5:*:*:*:*:*:*:* |
| iss | proventia_g_series_xpu | 22.6 | cpe:2.3:h:iss:proventia_g_series_xpu:22.6:*:*:*:*:*:*:* |
| iss | proventia_g_series_xpu | 22.7 | cpe:2.3:h:iss:proventia_g_series_xpu:22.7:*:*:*:*:*:*:* |
| iss | proventia_g_series_xpu | 22.8 | cpe:2.3:h:iss:proventia_g_series_xpu:22.8:*:*:*:*:*:*:* |
| iss | proventia_g_series_xpu | 22.9 | cpe:2.3:h:iss:proventia_g_series_xpu:22.9:*:*:*:*:*:*:* |
| iss | proventia_g_series_xpu | 22.10 | cpe:2.3:h:iss:proventia_g_series_xpu:22.10:*:*:*:*:*:*:* |
| iss | proventia_m_series_xpu | <= 1.9 | cpe:2.3:h:iss:proventia_m_series_xpu:*:*:*:*:*:*:*:* |
| iss | proventia_m_series_xpu | 1.1 | cpe:2.3:h:iss:proventia_m_series_xpu:1.1:*:*:*:*:*:*:* |
| iss | proventia_m_series_xpu | 1.2 | cpe:2.3:h:iss:proventia_m_series_xpu:1.2:*:*:*:*:*:*:* |
| iss | proventia_m_series_xpu | 1.3 | cpe:2.3:h:iss:proventia_m_series_xpu:1.3:*:*:*:*:*:*:* |
| iss | proventia_m_series_xpu | 1.4 | cpe:2.3:h:iss:proventia_m_series_xpu:1.4:*:*:*:*:*:*:* |
| iss | proventia_m_series_xpu | 1.5 | cpe:2.3:h:iss:proventia_m_series_xpu:1.5:*:*:*:*:*:*:* |
| iss | proventia_m_series_xpu | 1.6 | cpe:2.3:h:iss:proventia_m_series_xpu:1.6:*:*:*:*:*:*:* |
| iss | proventia_m_series_xpu | 1.7 | cpe:2.3:h:iss:proventia_m_series_xpu:1.7:*:*:*:*:*:*:* |
| iss | proventia_m_series_xpu | 1.8 | cpe:2.3:h:iss:proventia_m_series_xpu:1.8:*:*:*:*:*:*:* |