CWE-1247 3 CVEs MITRE definition ↗

CWE-1247: Improper Protection Against Voltage and Clock Glitches

Overview

CWE-1247 (Improper Protection Against Voltage and Clock Glitches) documents a weakness type used across vulnerability databases and security assessments. Use the sections below for definition, context, and mapped CVEs.

Security impact
Security impact: Depends on product and context; use CVE records, severity scores, and MITRE guidance to prioritize.

Description

The device does not contain or contains incorrectly implemented circuitry or sensors to detect and mitigate voltage and clock glitches and protect sensitive information or software contained on the device.

Applicable platforms

Kind Name Class Prevalence OS / CPE
language Not Language-Specific Undetermined
operating_system Not OS-Specific Undetermined
architecture Not Architecture-Specific Undetermined
technology ICS/OT Undetermined
technology System on Chip Undetermined
technology Power Management Hardware Undetermined
technology Clock/Counter Hardware Undetermined
technology Sensor Hardware Undetermined

Related CVEs in this database

These CVEs are mapped to this weakness in this database and kept for traceability and search.

CVE Published Summary
CVE-2025-54520 2025-09-24 Improper Protection Against Voltage and Clock Glitches in FPGA devices, could allow an attacker with physical access to undervolt the platform resulting in a loss of confidentiality.
CVE-2024-4760 2024-05-16 A voltage glitch during the startup of EEFC NVM controllers on Microchip SAM E70/S70/V70/V71, SAM G55, SAM 4C/4S/4N/4E, and SAM 3S/3N/3U microcontrollers allows access to the memory bus via the debug …
CVE-2022-31224 2022-09-12 Dell BIOS versions contain an Improper Protection Against Voltage and Clock Glitches vulnerability. An attacker with physical access to the system could potentially exploit this vulnerability by trigg…

Previous names

  • Missing Protection Against Voltage and Clock Glitches (2020-08-20)
  • Missing or Improperly Implemented Protection Against Voltage and Clock Glitches (2021-10-28)

Content submission

Name
Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi
Organization
Intel Corporation
Date
2020-02-12
Version
4.0

Content modifications

Date Name Version Importance Comment
2020-08-20 CWE Content Team 4.2 updated Demonstrative_Examples, Description, Name, Observed_Examples, Potential_Mitigations, Related_Attack_Patterns
2020-12-10 CWE Content Team 4.3 updated Relationships
2021-03-15 CWE Content Team 4.4 updated Functional_Areas
2021-10-28 CWE Content Team 4.6 updated Description, Detection_Factors, Name, References, Weakness_Ordinalities
2022-04-28 CWE Content Team 4.7 updated Applicable_Platforms, Relationships
2022-06-28 CWE Content Team 4.8 updated Applicable_Platforms, Relationships
2022-10-13 CWE Content Team 4.9 updated Demonstrative_Examples, References
2023-01-31 CWE Content Team 4.10 updated Applicable_Platforms, Related_Attack_Patterns, Relationships
2023-04-27 CWE Content Team 4.11 updated References, Relationships
2023-06-29 CWE Content Team 4.12 updated Mapping_Notes
2023-10-26 CWE Content Team 4.13 updated Observed_Examples
2025-09-09 CWE Content Team 4.18 updated Relationships
2025-12-11 CWE Content Team 4.19 updated Demonstrative_Examples

Contributions

Type Name Date Comment
Content Parbati K. Manna 2021-10-18 provided detection methods
cvelogic Threat Intelligence