CWE-1281 5 CVEs MITRE definition ↗

CWE-1281: Sequence of Processor Instructions Leads to Unexpected Behavior

Overview

CWE-1281 (Sequence of Processor Instructions Leads to Unexpected Behavior) documents a weakness type used across vulnerability databases and security assessments. Use the sections below for definition, context, and mapped CVEs.

Security impact
Security impact: Depends on product and context; use CVE records, severity scores, and MITRE guidance to prioritize.

Description

Specific combinations of processor instructions lead to undesirable behavior such as locking the processor until a hard reset performed.

Applicable platforms

Kind Name Class Prevalence OS / CPE
language Not Language-Specific Undetermined
operating_system Not OS-Specific Undetermined
architecture Not Architecture-Specific Undetermined
technology Not Technology-Specific Undetermined
technology Processor Hardware Undetermined

Related CVEs in this database

These CVEs are mapped to this weakness in this database and kept for traceability and search.

CVE Published Summary
CVE-2025-56301 2025-09-30 An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 (2025-01-29) allowing attackers to corrupt exception handling and privilege state transitions via a…
CVE-2025-22840 2025-08-12 Sequence of processor instructions leads to unexpected behavior for some Intel(R) Xeon(R) 6 Scalable processors may allow an authenticated user to potentially enable escalation of privilege via local …
CVE-2024-37020 2025-02-12 Sequence of processor instructions leads to unexpected behavior in the Intel(R) DSA V1.0 for some Intel(R) Xeon(R) Processors may allow an authenticated user to potentially enable denial of service vi…
CVE-2023-46103 2024-05-16 Sequence of processor instructions leads to unexpected behavior in Intel(R) Core(TM) Ultra Processors may allow an authenticated user to potentially enable denial of service via local access.
CVE-2023-23583 2023-11-14 Sequence of processor instructions leads to unexpected behavior for some Intel(R) Processors may allow an authenticated user to potentially enable escalation of privilege and/or information disclosure…

Previous names

  • Sequence of Processor Instructions Leads to Unexpected Behavior (Halt and Catch Fire) (2021-07-20)

Content submission

Name
Nicole Fern
Organization
Cycuity (originally submitted as Tortuga Logic)
Date
2020-05-15
Version
4.1

Content modifications

Date Name Version Importance Comment
2020-08-20 CWE Content Team 4.2 updated Related_Attack_Patterns
2021-03-15 CWE Content Team 4.4 updated Potential_Mitigations
2021-07-20 CWE Content Team 4.5 updated Name, Observed_Examples
2022-10-13 CWE Content Team 4.9 updated Applicable_Platforms, Demonstrative_Examples
2023-04-27 CWE Content Team 4.11 updated Demonstrative_Examples, Description, References, Relationships
2023-06-29 CWE Content Team 4.12 updated Demonstrative_Examples, Mapping_Notes, References
2023-10-26 CWE Content Team 4.13 updated Demonstrative_Examples, Observed_Examples
2025-12-11 CWE Content Team 4.19 updated Weakness_Ordinalities

Contributions

Type Name Date Comment
Content Shaza Zeitouni, Mohamadreza Rostami, Pouya Mahmoody, Ahmad-Reza Sadeghi 2023-06-21 suggested demonstrative example
Content Rahul Kande, Chen Chen, Jeyavijayan Rajendran 2023-06-21 suggested demonstrative example
Content Hareesh Khattri 2023-06-21 contributed to observed example
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