This page lists publicly disclosed CVE vulnerabilities affecting intel core_m (linked via NVD CPE). Each row includes severity scores, summaries, and publication dates to help identify and analyze security issues.
| CVE | Summary | Source | Max CVSS | EPSS % | Published | Updated |
|---|---|---|---|---|---|---|
| CVE-2018-3646 | Systems with microprocessors utilizing speculative execution and address translations may allow unauthorized disclosure of information residing in the L1 data cache to an attacker with local user access with guest OS privilege via a terminal page fault and a side-channel analysis. | [email protected] | 5.6 | 8.10% | 2018-08-14 | 2026-05-29 |
| CVE-2018-3620 | Systems with microprocessors utilizing speculative execution and address translations may allow unauthorized disclosure of information residing in the L1 data cache to an attacker with local user access via a terminal page fault and a side-channel analysis. | [email protected] | 5.6 | 5.58% | 2018-08-14 | 2026-05-29 |
| CVE-2018-3693 | Systems with microprocessors utilizing speculative execution and branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a speculative buffer overflow and side-channel analysis. | [email protected] | 5.6 | 8.42% | 2018-07-10 | 2024-11-21 |
| CVE-2018-3665 | System software utilizing Lazy FP state restore technique on systems using Intel Core-based microprocessors may potentially allow a local process to infer data from another process through a speculative execution side channel. | [email protected] | 5.6 | 0.61% | 2018-06-21 | 2024-11-21 |
| CVE-2018-3640 | Systems with microprocessors utilizing speculative execution and that perform speculative reads of system registers may allow unauthorized disclosure of system parameters to an attacker with local user access via a side-channel analysis, aka Rogue System Register Read (RSRE), Variant 3a. | [email protected] | 5.6 | 7.56% | 2018-05-22 | 2024-11-21 |
| CVE-2018-3639 | Systems with microprocessors utilizing speculative execution and speculative execution of memory reads before the addresses of all prior memory writes are known may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis, aka Speculative Store Bypass (SSB), Variant 4. | [email protected] | 5.5 | 60.63% | 2018-05-22 | 2026-05-29 |
| CVE-2018-9056 | Systems with microprocessors utilizing speculative execution may allow unauthorized disclosure of information to an attacker with local user access via a side-channel attack on the directional branch predictor, as demonstrated by a pattern history table (PHT), aka BranchScope. | [email protected] | 5.6 | 0.70% | 2018-03-27 | 2024-11-21 |
| CVE-2017-5754 | Systems with microprocessors utilizing speculative execution and indirect branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis of the data cache. | [email protected] | 5.6 | 84.17% | 2018-01-04 | 2026-05-28 |
| CVE-2017-5753 | Systems with microprocessors utilizing speculative execution and branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis. | [email protected] | 5.6 | 93.84% | 2018-01-04 | 2026-05-28 |
| CVE-2017-5715 | Systems with microprocessors utilizing speculative execution and indirect branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis. | [email protected] | 5.6 | 74.04% | 2018-01-04 | 2025-05-06 |